Minutes of CALICE Electronics Meeting, RAL, 11/03/04 ==================================================== Present: Adam Baird, Dan Bowerman, Paul Dauncey, Catherine Fry, Osman Zorba Minutes: Paul Matters arising: Progress was good enough in the last week that it was decided to take the equipment to Imperial directly after the meeting. The VME firmware version reported in the last minutes, 0x1100030D, is not the one which is loaded on the CERCs, i.e. 0x11000304. Paul has contacted Ed to find out whether the differences are significant w.r.t. Dave running the latest BE firmware. If needed, the VME code can be updated at Imperial. Note, the VME is not loaded from the CompactFlash. There is no progress on finding a suitable electronic logbook. The NIM-LVDS module was being tested this morning; there is not yet a cable to connect it to the back of the crate. Adam should send his passport details, etc, to Paul asap. Adam reported that RAL have already upgraded to Advantage V6.2. Hardware status: Adam reported on the findings of the power-up studies. Although the Xilinx spec says times of 200us are allowable, somewhere in the range of 2-50ms is probably more realistic. At present, the ramp-up time is 3ms and slowing this to 10ms would be safer. One thing which would be straightforward to try would be slowing down the ACE clock. This may not be related to the firmware boot problems. Osman sees the boards boot better from a literally cold board. One issue there might be that slower EPROMs than intended were used; Adam will check. SER001 has a very unreliable boot-up; it tends to come up for a short time (a few seconds to a minute) and then the clock disappears. However, it has been seen to stay up semi-indefinitely. One possibility is a bad solder joint which might not have been found by JTAG; this could be retested. The LEDs give no indication of the failure mode. This board will be left at RAL for now to be tested, although it is essential that it goes to Paris for the VFE tests in a few weeks. Adam has fixed the faulty DAC on FE5 for SER002. He replaced several missing components but also found two pins on the DAC with bad joints. It now appears to work correctly. The cause of the factor of two mismatch for the DAC->ADC loopback has not been investigated. Adam thinks it might be wrong values for the bias resistors but this needs to be checked. Jean-Charles Vanel sent a proposal for the differential range of the analogue input; he proposes the 0V option. Adam should reply about whether it is suitable asap. FE status: Osman showed some slides on his progress. The interface spec was found not to be correct, in that the HOLD needed to be inverted and SROUT required 36, not 18 multiplex clocks to emerge and a 37th to be turned off. (This is partially an issue with the VFE prototype; the final VFE version will need 19 clocks total.) He sees a large amount of ringing on the HOLD after the trigger, but this may be due to the lack of termination when the measurement was done. He measures the latency through the CERC from the DevBoard external trigger to the leading edge of the HOLD on the front panel SCSI connector (at minimum HOLD delay setting) to be 50ns, which is quite a large proportion of the 180ns total. 18ns is due to the FE; the rest appears to be the BE. This together with a large observed jitter might imply the BE is synching the trigger to a 40MHz clock; this must be checked with Matt. Including the FE-BE final interface, the FPGA is less than 50% full. In fact, the smaller (500) component would be around 50% full if this was used. However, there are two pins used (W16 and Y16, which are the two differential lines for the VFE ENABLE5) in the design which are not present in the 500 FPGA. These would need to be retracked to other pins. The design now sends a TCALIB signal for every trigger, when enabled. This was not the case when a short VFE with DAC test run was taken a few days before, when no signal was seen. This test needs to be repeated. From Catherine's plots (see below), it appears that the FE is reading the VFE chips on the VFE PCB as chips 2, 3, 8 and 9 (counting 0-11) with chip 3 faulty, whereas they were described by Julien as 1, 2, 11 and 12, with chip 12 faulty. The order of data into the FIFO should be the OUTPUTn order from the SCSI connector. The FIFO is being filled with extra data (corresponding to ~5 triggers) when the configuration constants are reloaded during a run. This only happens on the second and subsequent reloads, not the first. Flushing the data from the FIFOs before triggering seems to give sensible data from the triggers but slows down the readout substantially. The FE still reports the ADC is BUSY for the first sample from each ADC. A RS232-readable firmware version should be added to future designs. BE status: In the absence of both Matt and Dave, there was nothing to report on progress. The known problems are: o Although triggers generated by the BE and send to the FEs are seen and counted reliably, the external triggers generated by the DevBoard are not. Some of the FEs see the triggers and some do not each time. There could be some timing difference between the two modes. o The issue of rounding the trigger to a clock and/or the cause of the external trigger jitter needs to be investigated. o The code to fix the multiple userReadCommand0s needs to be installed and tested. o The VFE TYPE information reads back as a non-constant value. Data analysis: Paul showed some plots of an internal DAC loopback run for all eight FEs on SER002. They all show the same behaviour as the single FE shown at the previous meeting, i.e. non-linear below ~1000 DAC counts but then qualitatively good linear behaviour to the top end of the DAC. More analysis is needed to get quantitative limits on non-linearities over the whole range. Catherine showed some plots from a VFE run. 38 multiplex clocks (and hence samples) were taken, with the SRIN timed to be on the for second rising edge. Hence, the first sample should have been a baseline, the next 18 the gain=1 data, the next 18 the quiessent level and the last the same baseline. Data was taken with chips 2, 3, 8 and 9 (counting 0-11) from the VFE PCBs connected. A sine wave was applied to channel 10 (counting 0-37) of chip 2. Channels 1-18 in this system are the ones actually connected to pads. Chip 3, although connected, was dead. 100 events were taken with enable=0 gain=0, 100 at enable=0 gain=1, 100 at enable=1 gain=0 and 100 at enable=1 gain=1, although the correspondence of these to a high or low level needs to be checked. The means and the sigmas of these results and their associated errors were found for each channel of each chip for each set of 100 events. She plotted the sigma (noise) of chip against the channel number. These plots are labelled sigma_chip#_enable#_gain#. For the unconnected chips the noise is around 1.5 ADC counts. o For chip 2 (the one with the sine wave) it is around 50 for enable=0, gain=0/1 and around 15 for enable=1, gain=0/1. There appears to be a general trend for it to decrease from channels 1-18 (the ones connected to pads), but in channel 10 (the one with the sine wave) the noise is off the scale of the graph. The noise is also slightly higher in channel 11 than in the other channels, suggesting perhaps a correlation between channels 10 and 11. o For chip 3 (connected, but supposedly dead) the noise is slightly higher than the chips that are not connected, at around 6 instead of 1.5. o For chips 8 and 9, the other two connected chips, the noise is around 35 for enable=0 and around 12 for enable=1. It seems that changing gain from 0 to 1 has negligible effect at the moment. Since the noise in chip 2 channel 11 was slightly higher than expected, a plot was made of channel 10 (with the sine wave so expected to have high noise) against channel 11 to see if there was a correlation. This produced a kind of P shape. It seemed it was an ellipse, cut off at some lower bound on channel 10 (around -250), perhaps due to saturation. Similar plots were made for all adjacent channels to see if they appeared to be correlated. These are the files named 'chip2_chanY_chanX_'. Various shaped were obtained between the channels: (a) straight line (possibly a squashed ellipse), approximately same value in both channels; seen between channels 1-2, 7-8. (b) ellipse-shaped ring(s): seen between channels 2-3, 5-6, 8-9, 11-12, 13-14, 17-18. (c) ~2 clusters: seen between channels 3-4, 4-5. (d) rectangular-shaped distribution, not even: seen between channels 6-7, 12-13. (e) P-shape: seen between channels 9-10, 10-11. (f) 2 separate clusters, possibly rings: seen between channels 15-16, 16-17. It seems there is something happening between the channels (cross-talk?). Further work is required to understand what it is though. Dan showed some plots (see directory) of attempted fits to the ADC output from the board] when a sawtooth function was applied using a 'simple' signal generator. Paul, Osman and Adam had taken sets of data which: 1) Fully saturated the ADC 2) Went very close to the upper and lower ADC limits 3) Used ~50% of the available ADC range He examined each and there are postscript files in this directory which show each case. For each run, 20 'events' were taken and there is typically one event per page. 1) sum1078400972_Saturated.ps shows the saturated results. Each event clearly shows the saturated value. He needs to perform a fit to extract the upper and lower limits precisely. 2) sum1078400637_FullRange.ps shows sawtooth fits to the whole range. The fits seem to work reasonably well. He hasn't looked at the residuals (the difference between the fitted function and the data) yet but will report next week. The fit itself gives the upper and lower limits, a period and a phase. Pages 23, 24 and 25 show the fitted values. 3) sum1078401573_HalfRange.ps shows the half ADC range and similar fits, which again work reasonably well. Page 23, 24 and 25 again show the grouped fit results. He also tried to combine the different events in each sample into one fit, so theoretically giving better errors. ExampleMultFitWorking.eps and ExampleMultFitWorking_FullRange.eps show attempts to get the fit working. In both cases the events are added into the same histogram and so are effectively continuous with a phase change at the point where they go from one event to the next. The fit result seems fine, but using ROOT to show the fit on the screen gives problems and doesn't represent the data properly. List of tasks: The following items need to be done before Paris: o The full latency, including the NIM-LVDS module, needs to be measured. A first look at the module showed very unclean signals and a latency of order 50ns, which would make it unusable. The cable needs to be make also. o An external DAC loopback test should be done on several channels. o VFE tests without DAC to check for noise and crosstalk dependence on the multiplex and ADC timing settings. o VFE tests with DAC to see if any signal can be found and determine the correct HOLD timing setting. o The VFE TYPE and link array information needs to be able to be read back. Although not required for Paris, the BE is clearly now very far behind schedule and is very likely to cause a large delay if progress is not made very soon. The QDRs will not be mounted until after Paris. Next meeting: Imperial at 2pm on Wed 17 Mar, assuming Dave and Matt can make it. This could be a phone meeting as well for people who cannot attend in person if there is someone at Rob's office to take the calls.