Minutes of CALICE Electronics Meeting, RAL, 12/05/04 ==================================================== Present: Adam Baird, Paul Dauncey, Rob Halsall, Matt Warren, Osman Zorba Minutes: Paul Matters arising: There has not been much progress on analysing the remaining data from the April VFE tests; Paul and Dan Biwerman will be tackling this in the next week or so. Adam has not yet been out to Paris to investigate the noise problems. Paul is aiming to go out in the next week; possibly Mon (depending on cost) but definitely Wed-Fri. Adam will try to come along for the latter two or three days. It should be possible to bypass the slower components in the NIM-LVDS module to shorten the latency from 37ns to something like half this, i.e. ~20ns. Adam should take out as many of the pieces needed as possible so we are not dependent on much being available at Paris. Paul will contact Julien Fleury about the latency of the LVDS-TTL converter on the VFE PCB; note the 32ns quoted in the last meeting included the CERC-VFE cable, which was 3m and so would have contributed ~14ns of this; the VFE PCB part is therefore around 18ns. SER001 has been tested with the RS232 link and works OK at RAL. This could mean something on the board is very marginal and so works in one environment but not the other. One suggestion was that the VME reset (from the VME FPGA) might not be in a definite state. No VME access is done at Paris during tests so it was certainly not set; however, the same is true at RAL. (Note, the VME version is the same as the firmware update had not been done.) Paul will test this by sending a VME reset before trying the boards when at Paris. Another possibility is of course the grounding; Matt and Adam have made up a cable for the devboard-crate connection which includes the ground. A possibly related issue is the failure of FPGA loading on power-up; Adam has found the FPGAs load every time with SER001 in the CMS crate, but Matt found this was not the case in the mini-crate. While this could be due to the power-up ramp speed being different, Paul found the FPGAs did not load for both SER001 and SER002 in the crate in Paris, which should be equivalent to the CMS crate at RAL. Paul also found the reset button did not work; this should be checked with the CMS crate after the meeting. A further complication is that Saeed added a wire after finding the hot-swap LED was on continuously. The new wire makes the 1.5V reset wait until the 12V supply is fully ramped. There was some doubt about the validity of this change; Adam thinks it might bypass the power supply control and so is a temporary cludge at best. It is not clear if this change could have cured the load problems. The QDRs have been mounted on SER001, but the VME firmware upgrade still needs to be done before it is taken to Paris next week. The ADC and DAC ranges will be modified (as discussed below). We will need 3 (or 4 including a spare) cables of the same length for the next round of VFE tests. Adam will borrow some to take out next week. Paul has not yet heard from Bernard Bouquet who is looking into the cable lengths for the final system. A replacement USB CF writer should be ordered by RAL asap, preferably in time to take out next week. Paul will in any case take out his PCI card CF writer for his laptop and Adam will have a look at the broken USB module to see if it can be fixed while at Paris. Adam had sent Paul an email with the location of the final version of the schematics, as used for the prototype; Paul will put this on the web. A "user guide" write-up of the prototype is still needed, to collect the material which is spread over Adam's web pages into one place. Paul has started trying to reorganise the documentation web page but has only done the VFE interface document so far. Dave Mercer was supposed to have visited RAL in the last two weeks to talk to Saeed and try loading a simple version of the BE firmware, but he has not been in contact (nor been seen at RAL) since the last meeting. Adam's problem reports page now has a quite long list of (mainly minor) issues with the prototype board, although most do not lead to changes to the PCB itself. The changes which would be needed have to be understood so that subsequently the schematics can be updated. Rob and Adam wanted to be sure they had all required changes defined before going back to the Drawing Office for relayout, although this then requires that more time be allowed for the layout. It is still essential that the boards are ready for the next round of fabrication by the end of July. Given the number of changes, it might be prudent to only assemble two boards immediately as an effective "preproduction", with the rest made up around a month later. This would be acceptable given the overall ECAL schedule, as the critical date of the first ten layers (which need two boards to be fully read out) being available in September is what sets the schedule. The remaining twenty layers will become ready over the following month. Rob warned that the last FED assembly (at DDI) took 6 weeks; this would clearly be unacceptable for us. ADC and DAC ranges: The aim here is to adjust the ADC and/or DAC ranges to better match the VFE requirements but without any major changes to the PCB; i.e. with what can be done purely through adjusting the resistor values used. The VFE PCB differential output voltage which the CERC could take in is currently in the range -2.5V to +2.5V. However, the VFE PCB design means the output is never driven negative by any significant amount; the signals are nominally 0 to +2.5V although a tolerance of +/- 0.1V per channel means the actual range expected is roughly -0.1V to +2.6V. Adam said there was no way the CERC ADC input range could be recentred to coincide with this positive displaced range, without a redesign of the PCB. It is possible for the VFE PCB to be easily adjusted (with a resistor change) to shift the output range to be centred around zero, i.e. -1.35V to +1.35V including the tolerance. However, Jean-Charles Vanel will be doing a first calibration of each board with a NI card which has a very limited dynamic range. This then requires the pedestal to be close to zero, not around -1.3V. Adam has discussed this with Julien and Jean-Charles and hopes they can come up with a scheme to allow the resistor (and hence output range) to be quickly and reversibly changed, e.g. via a jumper or similar. If this can be done, then the CERC ADC input range could be adjusted to better match the VFE PCB output. To be sure of seeing the complete VFE range into saturation, we would aim for a range of something like -1.5V to +1.5V, which means a gain increase compared to now of 2.5/1.5 ~ 1.67. However, if the VFE PCB is left as it is now, then the nominal CERC range is not quite high enough at the top end to be sure of seeing the VFE in saturation, given the tolerance. Hence, we should then aim for a range of around -2.7V to +2.7V (where almost the whole of the lower half will never be used). This would require a gain decrease of around 2.5/2.7 ~ 0.93. The 16-bit ADC currently gives a noise (in the best case) of around 8 ADC counts, so this small gain change should not signficantly affect the digitisation noise contribution. The latter change is small enough that we should not bother adjusting the prototypes. However, the former is worth checking, so Adam will change the ADC settings on all 12 ADC inputs for one of the FE modules on SER001 before it is taken to Paris next week. Then, if a VFE PCB is made with the adjusted range, we can check things look as we expect. The other issue is the DAC. The calibration circuit on VFE PCB V3 will have been changed, so that it is not clear how our DAC range maps onto the VFE channel response. To be sure that we can drive the VFE outputs to their full range, the DAC on the FE module with the adjusted ADCs will also be modified to give an output of 0.0V to 4.0V (compared with 0.0V to 1.25V now). Firmware progress: Osman showed some slides on the FE status (see his talk). He is still puzzled by the DAC corruption and it was suggested that he try using the logic analyser outputs, given that he has had some problems with Chipscope. He is also still concerned about using internal pull-ups for the VFE type and link array inputs; it seems unlikely this will work well and so external pull-ups may be required in the production version. He has also got some code from Saeed to access the LM82 temperature sensor. Osman will produce a new version to test in Paris next week. Of the list given in the last minutes, he has added the link array readout (at register 51) and the DAC readout order should now effectively be correct. The ADC BUSY problem is not fixed, the DAC value may still be corrupted, the HOLD latency will be the same and there will still be separate FE version numbers for Osman's code and Matt's RS232 code. The ADC output order will be compacted into a smaller data volume, which will help both with storage eventually in the 8 MByte memories as well as RS232 readout speed immediately. Matt has a new version of both the devboard firmware (V8, which will be tested next week) and the BE code. He has cleaned up the trigger distribution significantly, given that there were problems with the reliability of the trigger in V3.6_2. He has also added a BE FIFO to store the trigger input history, allowing an indication of whether there was any other activity around the trigger. He will look at implementing some simple write/read checks for the QDRs. He would also like to test the FE-BE lines and the BE-backplane lines. All have been checked (effectively DC) by the original JTAG tests, so this would be looking for problems when used at speed. Hence, something like looping back a 40MHz clock and counting to check for consistency would be useful. Adam pointed out that some of the LVDS pairs to the backplane do not come out on adjacent pins. This is not ideal and so these tests are needed to check for crosstalk here. Of the other items on the list; the board serial number is supposed to be programmed into an EPROM readable by the VME FPGA. Paul was pretty sure this was not available in the VME version used at present on the CERCs but it clearly not a BE issue. After Osman's code to access the LM82 sensor is tested, Matt will try installing this in the BE. As stated above, nothing has been heard from Dave Mercer on the longer-term BE progress. Paris organisation: The following will be taken out by Adam next week; o SER001 with the ADC and DAC modifications, the VME firmware upgrade and the serial number PROM programmed. o 3 (or 4) SCSI cables of the same length. o The USB CF writer, if it arrives in time. o The new devboard-backplane cable with grounding. o Any bits and pieces needed for the NIM-LVDS module modifications. Paul will take out; o The PCI CF writer, and his laptop to be able to use it. o The RAL devboard, which Matt has reprogrammed to firmware V8. Next meeting: 11am on Wed 26 May at RAL.