TLU_Master Project Status (02/16/2010 - 19:37:18) | |||
Project File: | TLU_Master.ise | Current State: | Programming File Generated |
Module Name: | top_master_controller |
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Target Device: | xc3s1000-4fg676 |
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Product Version: | ISE 10.1 - Foundation Simulator |
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All Signals Completely Routed |
Design Goal: | Balanced |
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All Constraints Met |
Design Strategy: | Xilinx Default (unlocked) |
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0 (Timing Report) |
TLU_Master Partition Summary | [-] | |||
No partition information was found. |
Device Utilization Summary | [-] | ||||
Logic Utilization | Used | Available | Utilization | Note(s) | |
Total Number Slice Registers | 2,029 | 15,360 | 13% | ||
Number used as Flip Flops | 2,027 | ||||
Number used as Latches | 2 | ||||
Number of 4 input LUTs | 2,319 | 15,360 | 15% | ||
Logic Distribution | |||||
Number of occupied Slices | 1,935 | 7,680 | 25% | ||
Number of Slices containing only related logic | 1,935 | 1,935 | 100% | ||
Number of Slices containing unrelated logic | 0 | 1,935 | 0% | ||
Total Number of 4 input LUTs | 2,551 | 15,360 | 16% | ||
Number used as logic | 2,318 | ||||
Number used as a route-thru | 232 | ||||
Number used as Shift registers | 1 | ||||
Number of bonded IOBs | 122 | 391 | 31% | ||
IOB Flip Flops | 32 | ||||
IOB Master Pads | 8 | ||||
IOB Slave Pads | 8 | ||||
Number of RAMB16s | 10 | 24 | 41% | ||
Number of BUFGMUXs | 4 | 8 | 50% | ||
Number of DCMs | 2 | 4 | 50% |
Performance Summary | [-] | |||
Final Timing Score: | 0 | Pinout Data: | Pinout Report | |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
Timing Constraints: | All Constraints Met |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Tue 16. Feb 19:34:35 2010 | ||||
Translation Report | Current | Tue 16. Feb 19:35:02 2010 | ||||
Map Report | Current | Tue 16. Feb 19:35:29 2010 | ||||
Place and Route Report | Current | Tue 16. Feb 19:36:36 2010 | ||||
Static Timing Report | Current | Tue 16. Feb 19:36:52 2010 | ||||
Bitgen Report | Current | Tue 16. Feb 19:37:10 2010 |