TLU_Master Project Status (02/26/2010 - 16:09:18)
Project File: TLU_Master.ise Current State: Programming File Generated
Module Name: top_master_controller
  • Errors:
No Errors
Target Device: xc3s1000-4fg676
  • Warnings:
462 Warnings
Product Version: ISE 10.1 - Foundation Simulator
  • Routing Results:
All Signals Completely Routed
Design Goal: Balanced
  • Timing Constraints:
All Constraints Met
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
(Timing Report)
 
TLU_Master Partition Summary [-]
No partition information was found.
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Total Number Slice Registers 2,058 15,360 13%  
    Number used as Flip Flops 2,056      
    Number used as Latches 2      
Number of 4 input LUTs 2,355 15,360 15%  
Logic Distribution     
Number of occupied Slices 1,957 7,680 25%  
    Number of Slices containing only related logic 1,957 1,957 100%  
    Number of Slices containing unrelated logic 0 1,957 0%  
Total Number of 4 input LUTs 2,587 15,360 16%  
    Number used as logic 2,354      
    Number used as a route-thru 232      
    Number used as Shift registers 1      
Number of bonded IOBs 128 391 32%  
    IOB Flip Flops 32      
    IOB Master Pads 8      
    IOB Slave Pads 8      
Number of RAMB16s 10 24 41%  
Number of BUFGMUXs 4 8 50%  
Number of DCMs 2 4 50%  
 
Performance Summary [-]
Final Timing Score: 0 Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentFri 26. Feb 16:06:15 20100451 Warnings50 Infos
Translation ReportCurrentFri 26. Feb 16:06:41 2010000
Map ReportCurrentFri 26. Feb 16:07:42 201006 Warnings8 Infos
Place and Route ReportCurrentFri 26. Feb 16:08:35 201005 Warnings2 Infos
Static Timing ReportCurrentFri 26. Feb 16:08:50 2010002 Infos
Bitgen ReportCurrentFri 26. Feb 16:09:09 201003 Warnings1 Info

Date Generated: 02/26/2010 - 16:09:18