CALICE-UK MAPS IDR1 Home Page
Contains documents, minutes, talks, etc., from the CALICE-UK MAPS IDR1; Part 1 on 19 Dec 2006, Part 2 on 25 Jan 2007
- Organisation
- Agenda, part 1
- Introduction
- Shaper pixel design
- Sampler pixel design
- Comparator (common to both)
- Agenda, part 2
- Introduction
(ppt,
pdf)
- Row-controller logic
- SRAM storage and readout
- Mask/trim programming
- Top level (clock buffering, signal propagation, maximum
operating rates, pad cells)
- Schematics (protected)
- Presample and preshape schematics
(pdf)
- Top level
(pdf)
- Simulation results
- Presample
(pdf)
- Preshape
(pdf)
- Comparator
(pdf)
- Logic and top level
(pdf)
- Outcome
- Notes:
part 1 (txt),
part 2 (txt)
- Review approval forms:
part 1
(doc,
pdf),
part 2
(doc,
pdf)
Go to the CALICE-UK home page